An electrically programmable ROM (EPROM) implements non-volatile storage of data using a storage transistor having a so-called floating gate. The storage transistor, or memory cell, is programmed by having hot electrons injected into a floating gate to cause a substantial shift in the threshold voltage of the storage transistor. This technique is generally termed hot electron tunneling. Under high gate and high drain voltages, electrons gain sufficient energy to jump the silicon-silicon dioxide energy barrier, penetrating the oxide and flowing to the floating gate, which is completely surrounded by oxide.
To implement the hot electron tunneling during the programming process, a voltage higher than the input voltage is required. To generate the high voltage necessary to realize the high current path, a pump circuit is generally implemented.
Another technique, FN tunneling, is a quantum-mechanical effect which allows electrons to pass through the energy barrier at the silicon-silicon dioxide interface. While the energy required for the electrons to pass this barrier is much lower than the energy required for hot electron injection programming, a pump circuit is still generally required.
It is well known to produce a pump that generates a high voltage pump output from a single input. Generally, if more than one input is required to generate high voltage pump outputs, separate pump circuits would be required. The implementation of separate pump circuits would require more chip real estate, which is generally undesirable with the goal of efficient use of device area. This is particularly true in very large scale integration (VLSI) technology.
FIG. 1 is a prior art scheme showing a single input used to generate a high voltage pump output. The pump 10 generally comprises an input Vpp, an oscillator input Ph and a output Pumpout. The pump 10 generally takes the input Vpp and increases it by a predetermined voltage amount to produce the output Pumpout.
FIG. 2 is a more detailed block diagram of a prior scheme showing a single input used to generate a high voltage output Pumpout. The pump 10 generally comprises an initialization circuit 11, an oscillator circuit 12 and a clamp circuit 13. The oscillator circuit 12 is shown as having two inputs PhA and PhB. The dual oscillator inputs PhA and PhB generally provide the best results. The initialization circuit 11 provides information that is used by the oscillator circuit 12 to initialize the internal nodes of the pump. The clamp block 13 prevents the output Pumpout from exceeding the voltage to be greater than the desired voltage.
FIG. 3 is a prior art scheme showing the circuitry used to generate a high voltage pump output from a single input. The pump 10 generally comprises an input PhA, an input PhB, an input Vpp and an output Pumpout. The pump 10 generally comprises a capacitively coupled transistor 14, a capacitively coupled transistor 15, a transistor 16, a transistor 18, a transistor 20, a transistor 22, a transistor 24, a transistor 26, a transistor 30 and a transistor 32. The input PhA is an oscillator input that is capacitively coupled through transistor 14 to both the drain and the gate of the transistor 18. The input PhB is an oscillator input that is capacitively coupled through transistor 15 to both the drain and the gate of the transistor 20. A single oscillator input could be used in place of the input PhA and PhB. However, it is generally accepted by those skilled in the art that a dual oscillator input configuration provides better results. On the positive cycle of the oscillation of the input PhA, the capacitively coupled transistor 14 pumps the voltage that is presented to the capacitively coupled node A. A similar charging occurs with input PhB and capacitively coupled transistor 15 on node B. The transistors 16, 18, 20, 22, 24, 26, 30 and 32 are each configurated as diodes since either the source or drain is coupled directly to the gate. The drains of the transistors 16, 18 and 20 are cascaded together. The drain of the transistor 16 receives an input from the input Vpp. The source of the transistor 20 is connected to the output Pumpout.
The input PhA is also presented to a capacitively coupled transistor 38. The input PhB is also presented to a capacitively coupled transistor 36. An output of the capacitively coupled transistor is presented to both the drain and the gate of the transistor 24 on node C. The output of the capacitively coupled transistor 36 is presented to both the drain and the gate of the transistor 26 on node D. The transistor 22 has a drain that is connected to the input Vpp. The source of the transistor 26 is connected to the output Pumpout. The sources and drains of the transistors 22, 24 and 26 are cascaded together. The transistor 30 receives an input from the input Vpp. The drain of the transistor 32 is connected to the output Pumpout. The drains and sources of the transistors 30 and 32 are cascaded together. The gate of the transistor 30 is connected to both the drain of the transistor 30 and the source of the transistor 32. The gate of the transistor 32 is coupled to the drain of the transistor 32. The input Vpp has three independent paths to the output Pumpout. The first path is through transistor 30 and the transistor 32. The transistor 30 and the transistor 32 provide a clamping effect on the output Pumpout. The voltage across the transistor 30 and transistor 32 is equal to Vpp+2Vtn, where Vtn equals the threshold voltage across a particular transistor 30 or 32. This clamping effect takes place since the transistors 30 and 32 are configured in reverse diode conditions. Effectively, the voltage across the transistors 30 and 32 is limited accordingly. The second path is through the transistor 16, the transistor 18 and the transistor 20. Before the oscillator is turned on the nodes A and C are at Vpp-Vtn and the output Pumpout is at Vpp-3Vtn. When the oscillator turns on the nodes A, B, C and D start pumping higher. The output Pumpout increases in voltage from Vpp-3Vtn and gets clamped by devices 30 and 32 at a voltage Vpp+2Vtn. The devices 16 and 20 are off at this time and the nodes A and C are pumped up to a voltage Vpp+4tn. The nodes B and D are pumped up to a voltage Vpp+3Vtn. It should be appreciated that the capacitively coupled transistors 14, 16, 36 and 38 take up the majority of the chip real estate of the pump circuit 10. To produce a pump circuit 10 that produces a Pumpout in response to more than one input, each of the transistors 14-32 would have to be duplicated for each input. The duplication of the capacitively coupled transistors 14, 16, 36 and 38 would be undesirable in view of the goal of reducing chip real estate.